Critical IC mineral concerns; wafer shipments shrink; Europe bets big on AI; new ultrasonic cleaner; high-speed DRAM test; ...

A new technical paper titled “Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies” was published by researchers at Arizona State University. Abstract ...

Linear normalization, which is most common, involves shifting the number axis so the data is balanced around zero, and then ...

Chiplet design engineers have complex new considerations compared to PCB concepts. Maintaining the quality and reliability of ...

AI-driven automation, tighter design-test collaboration, and evolving BiST techniques are redefining DFT strategies.

ARFM-Driven Row Hammer Defense with Unveiling the Threat of Short tRC Patterns” was published by researchers at KAIST and Sk ...

A new technical paper titled “Exploring Uncore Frequency Scaling for Heterogeneous Computing” was published by researchers at ...

Manufacturing is something the semiconductor industry wanted to forget about for decades. It’s now front and center and ...

Rigorous testing is still required, but an abstraction layer can significantly reduce errors in the fab while optimizing ...

A Wafer-Scale LLM Inference System” was published by researchers at University of Edinburgh and Microsoft Research. Abstract ...

Introduction to LLMs and SLMs, as well as the market dynamics around widescale adoption of Gen AI at the edge.

From new applications to new cooling technologies, the data center industry is at a turning point. A panel of thermal and ...